1. Field of the Invention
The present invention relates to a package structure for a semiconductor chip, including a substrate on which a semiconductor chip is mounted via an underfiller filling between the substrate and the chip.
2. Description of the Related Art
FIGS. 11 and 12 show a known package structure of a semiconductor chip.
A substrate 10 has pads 12 formed thereon and a semiconductor chip 20 has electrodes connected by soldering etc. to the pads 12 through bumps 30 of solder or the like. An underfiller 40 of a cured resin fills a space between the semiconductor chip 20 and the underlying substrate 10 and also bonds the semiconductor chip 20 and the substrate 10. The substrate 10 is formed of epoxy or an other resin having a low permittivity and has circuit wiring (not shown) formed thereon and designed for transmitting high frequency signals without significant loss.
When a thermal stress is generated by a difference between thermal expansion coefficients of the semiconductor chip 20, typically of silicon, and the substrate 10, of resin, and acts between the chip 20 and the substrate 10, the underfiller 40 bonding the chip 20 and the substrate 10 prevents separation between the pads 12 of the substrate 10 and the electrodes of the chip 20, in which the electrodes are connected to the pads 12 through the bumps 30, to ensure good electrical connection between the semiconductor chip 20 and the pads 12.
The underfiller 40 consists of a resin containing a small amount of filler agents such as silicone and having good fluidity, because a space between the semiconductor chip 20 and the substrate can be as small as 80 to 100 .mu.m and a resin to be filled in the space must have a low viscosity, i.e., a high fluidity.
However, an underfiller 40 formed by curing a resin containing a small amount of filler agents and having a high fluidity has a thermal expansion coefficient greater than that of the semiconductor chip 20 or the resin substrate 10.
For example, a semiconductor chip 20 of silicon has a thermal expansion coefficient of 3.4 ppm/.degree. C. and a substrate 10 of an FR-4 resin has a thermal expansion coefficient of 15 ppm/.degree. C., whereas the above-mentioned underfiller 40 has a thermal expansion coefficient of 23 ppm/.degree. C.
When the semiconductor chip 20, the underfiller 40 and the substrate 10 are subject to heat generated by the semiconductor chip 20 etc., the differencs between thermal expansion coefficients of these three members generates thermal stress between these three members to cause distortion of the substrate 10 such that upward depression in the form of an arc etc. occurs in the lower surface of the substrate 10 in a portion underneath the semiconductor chip 20, so that electrical connection cannot properly achieved between pads on the depressed lower surface of the semiconductor chip 20 and pads on a separate mother board. The thermal stress acting between the substrate 10 and the underfiller 40 can also cause fracture of the fragile semiconductor chip 20.
In the conventional package structure shown in FIGS. 11 and 12, a rectangular frame 50 of copper or other stiff metal is secured on the substrate 10 to surround the portion of the substrate 10 in which the semiconductor chip 20 is mounted, thereby mitigating thermal stress exerted on the substrate 10.
However, this cannot provide a satisfactory solution to the problems that depression occurs in the lower surface of the substrate 10 in a portion underneath the semiconductor chip 20 or that large stress is exerted on the semiconductor chip 20. This is particularly significant for the case in which a large size semiconductor chip 20 having sides of 10 mm or more is mounted on a thin substrate 10.